Metal/High-k transistors formed by damascene process

Article Abstract:

Toshiba researchers have developed a damascene gate that process is claimed to lead to easier production of metal/high-k gate transistors. The process requires a dummy gate mask to ion-implant the source and drain. The dummy gate is them removed without resulting in any damage to the underlying layer. The metal gate is patterned by damascene, through which the gate electrode is self-aligned with the gate groove.

Toshiba Corp.

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Transistors go ballistic at Bell Labs

Article Abstract:

AT and T Bell Laboratories Inc researchers found that 'ballistic nontransistor' could increase the life of existing transistor technology. Recent studies were able to establish that transistor drive current could go 'ballistic' when the channel length was extremely small and the gate dielectric very smooth. The ballistic effect of electrons going through the channel is similar to a ball going through a pinball game, according to Bell Labs researcher Greg Timp.

Product information, AT&T Bell Laboratories Inc.

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Dual-damascene challenges dielectric etch

Article Abstract:

The advent of copper and low-k dielectrics poses various difficulties in the etch process, giving way to another alternative, a new solution called dual-damascene processing. The process involves cutting a trench or canal into the dielectric and inlaying it with metal. Manufacturers are already looking into three damascene process approaches, namely, the via-first sequence, the trench-first process and the buried-via or self-aligned process.

Semiconductor Devices

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