New technology for removing post etch residues
Article Abstract:
GaSonics International of San Jose, CA, has come up with a dry cleaning process that improves the removal of post etch residue. The method, called densified fluid cleaning (DFC), uses densified gases at temperatures of 30-40 degrees centigrade at 200-400 psi. The DFC method, when used with microwave downstream plasma, has been found to improve the removal of metallics and particles from computer chip wafers. According to Dr. Vladimir Starov, GaSonics' director of corporate technology, the DFC-enhanced cleaning process cuts oxide loss associated with other cleaning methods.
Comment:
Comes up with a dry cleaning process that improves the removal of post etch residue
Publication Name: Semiconductor International
Subject: Electronics and electrical industries
ISSN: 0163-3767
Year: 1998
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High-selectivity silicon nitride etch process
Article Abstract:
Very high-selectivity silicon nitride etch techniques are being used on an isotopic etcher employing a downstream, inductively coupled plasma system. Such methods are required to meet the needs of local oxidation of silicon (LOCOS) and shallow trench isolation (STI) applications. A nitride rate of 500 A/min facilitates an etch selectivity of LPCVD nitride to thermal oxide higher than 40:1. For a nitride-to-oxide selectivity higher than 12:1 with a nitride etch rate of around 1,200 A/min, a flourine-based etching chemistry was optimized.
Comment:
Very high-selectivity silicon nitride etch techniques are used on isotopic etcher employing a plasma system
Publication Name: Semiconductor International
Subject: Electronics and electrical industries
ISSN: 0163-3767
Year: 1998
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Consortium to tackle Cu etch, deposition and CMP needs
Article Abstract:
Novellus of San Jose, CA, has agreed to a strategic partnership with Lam Research of Freemont, CA, and Integrated Process Equipment Corp. (IPEC) of San Jose, CA. The alliance was formed to develop a wide range of integrated etch and deposition solutions for advanced copper damascene interconnect structures in future semiconductor devices. The alliance was also formed to resolve CMP issues that are expected to be encountered with the shift to better performing copper devices.
Comment:
Agrees to a strategic partnership w/ Novellus of San Jose, CA, and Lam Research of Freemont, CA
Publication Name: Semiconductor International
Subject: Electronics and electrical industries
ISSN: 0163-3767
Year: 1998
User Contributions:
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