A framework for distributed VLSI simulation on a network of workstations

Article Abstract:

A distributed framework for logic simulation is presented. Switch-level simulation has been mapped to a distributed platform using a network of workstations on an Ethernet bus. Model parallelism is used with preprocessing to partition the circuit to be simulated among the processors. The simulation algorithm is decoupled from the communication layers to ensure easy portability. We have proposed a high level pipelining scheme with multiple buffers to overcome the effects of a low bandwidth network. Speedups of up to 4.1 with 5 processors have been obtained for medium sized ISCAS benchmark circuits. The speedups achieved using distributed simulation are very close to that obtained by the same switch-level simulator implemented on a shared memory parallel machine. Novel techniques to improve the performance of distributed simulation have also been implemented on a shared memory parallel machine. (Reprinted by permission of the publisher.)

Electronic computers, Prepackaged software, Algorithms, Algorithm, Parallel processing, Network architectures, Workstations, Network Architecture, Performance, Distributed Systems, Pipelining

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Process-dependent circuit modeling and simulation of SOIJFETs: digital VLSI applications

Article Abstract:

Accurate circuit modeling and simulation of Silicon-on-Insulator (SOI) enhancement and depletion Junction Field-Effect transistors (JFETs) is presented. The nonuniformity in FET device parameters along the channel depth (due to fabrication processes), is taken into account. This is typical in SOI and other thin-film structures. Since SOI fabrication processes parameters are represented, in our model, by a closed form mobility variation, improved model accuracy is guaranteed. Simulation results are found to be within less than 3% of actual measurements. Small-signal circuit-model parameters are determined for SOI FJETs and then evaluated for further logic applications. Inverters with a channel Enhancement-JFET (E-JFET) drivers and n-channel depletion-JFET loads (E/D inverters) are also considered with different supply voltage values, device parameters and digital applications. (Reprinted by permission of the publisher.)

Circuit design, Thin films, Field effect transistors, Modeling, Data modeling software, Logic circuits, Logic Circuitry, Field-Effect Transistors

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