Fast interfaces for DRAMs: the fundamental circuitry between a device's interior logic and its external pins must evolve to meet new speed and power needs

Article Abstract:

The interface between DRAMs and processors must support speeds in at least the 100-500-MHz range if the two chip types are to trade data at close to top speed. So far, none of the popular interfaces can do this while conserving power and costs. One of the limits is that rail-to-rail swing consumes too much power. Output drivers running at 100 MHz each must dissipate over 100 mW to drive a 100-pF lumped load rail to rail with 3.3-V supplies, while each 100-MHz DRAM could have up to 16 output drivers operating at once, dissipating over 1.6 W. Another limitation stems from the failure to consistently match emitter-coupled logic (ECL) with FET devices. New proposals for achieving ECL's low swing and ability to drive terminated lines with optimized MOS circuits include supplying a set of simulation parameters for a circuit's output drivers.

Usage, Microprocessor, CPUs (Central processing units), Microprocessors, Communications protocols, Connectivity, Data Transfer Rate

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Center-tap terminated interface

Article Abstract:

The center-tap terminated (CTT) interface is an evolutionary, backward-compatible standard designed to ease the transition to new speed requirements. CTT drivers provide regular rail-to-rail swings when used unterminated in short-run situations, and CTT receivers have standard input threshold levels. However, the drivers automatically adjust to a restricted swing with a termination voltage near mid-level for longer runs where termination is essential. The elements needed for CTT include input buffers using internal reference levels. The reference levels are supplied externally, which allows the minimum high-input level and maximum low-input level to be tightened to plus/minus 200 mV. CTT's backward compatibility forces slightly higher power dissipation, while its benefits include lower system power from symmetrical drives.

Implementation, Performance/Cost Relationship

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Synchronous dynamic RAM

Article Abstract:

Synchronous DRAM, a chip that produces data rates of 500M-bps, is an evolutionary approach to high-speed memory that ties together many of the techniques developed to augment memory transfers. Synchronous DRAM manufacturers are addressing concerns regarding processor speed by building 16M-bit capacity into their designs, whereby the DRAM latches information in and out under the control of the system clock. The processor can perform other tasks while the RAM is processing its requests, since the processor knows how many clock cycles it takes for the DRAM to respond. A single synchronous DRAM chip can combine burst and wrap modes and interleaved banks and run at up to 400-500 megahertz.

Circuit Design, Synchronous

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