The environment, health and safety side of copper metalization
Article Abstract:
Motorola has developed a new technology called the Advanced Products Research and Development Laboratory (APRDL) that addresses the environment, health and safety impacts before processes are transferred to manufacturing. Motorola has completely evaluated the copper metalization processes and developed a strategy for protecting the environment, its employees and the managing of all waste streams. The company has designed an electrowinning system to handle concentrated copper wastes and is effective in treating concentrates from both the development and the manufacturing fabs.
Comment:
Developes the APRDL that addresses the environment, health & safety impacts before processes are transferred to manufacturing
Publication Name: Semiconductor International
Subject: Electronics and electrical industries
ISSN: 0163-3767
Year: 1998
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LSI to build new fab in Japan
Article Abstract:
LSI Logic of Milpitas, CA, plans to build a manufacturing facility in Tsukuba, Japan, to produce ICs for digital home electronics. Initial production of the facility is scheduled at 20,000 of 20 nm wafers per month and eventually will include 130 nm architectures by year 2000. The plant is expected to cost more than 758 million yen. The facility will be the third one to be built by LSI's subsidiary, LSI Logic Japan Semiconductors. The other fabs are producing 350 nm architectures on 150 nm wafers. LSI has began the production of 250 nm devices in its Gresham, OR, plant.
Comment:
To build a manufacturing facility in Tsukuba, Japan, to produce ICs for digital home electronics
Publication Name: Semiconductor International
Subject: Electronics and electrical industries
ISSN: 0163-3767
Year: 1998
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Pursuing the perfect low-k dielectric
Article Abstract:
The use of low-k dielectric interconnects has received a boost with the integration of such device structures as SiLK, HSQ, VECOX, FLARE, BCD and inorganic and organic VCD film for use in the crucial k = 2.5 field. While the choice of copper damascene by chip makers such as Motorola and IBM was viewed as a setback for low-k materials, the move by the industry to implement k = 3.0 to 4.0 at 0.18 micrometer and k = 2.5 to 3.0 at 0.13 micrometer is seen as an encouraging development for low-k.
Publication Name: Semiconductor International
Subject: Electronics and electrical industries
ISSN: 0163-3767
Year: 1999
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