Embedded DRAM technology: opportunities and challenges.((dynamic random access memory)(includes related article on DRAM and a graphics controller on one chip)
Article Abstract:
Embedded DRAM technology brings both opportunities and challenges to designers who must develop system-level designs to have DRAM and logic on one IC. They can put more memory bandwidth and excellent performance into a system-level design with such arrangements, but redesigning is needed instead of just mapping existing designs onto larger chips with lower yields at greater cost. Gate densities in the 0.18-micrometer generation are to be around 100,000/sq mm and just the number of gates makes it necessary to use a system-level approach. By 2003, the market for on-chip systems featuring embedded DRAM is likely to be about $6 bil and the ASIC market more than $40 bil. Built-in self-test (BIST) will be an important capability.
Publication Name: IEEE Spectrum
Subject: Engineering and manufacturing industries
ISSN: 0018-9235
Year: 1999
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Software for the 'testability police'
Article Abstract:
Design Compiler (DC) Expert Plus from Synopsys Inc. is being used by Adaptec for its group in charge of design-for-test (DFT) planning at the architecture level and for DFT implementation and review at various levels. The group also uses TestGen, now from Synopsys, which has acquired Sunrise, the originator. Test Gen is used for automatic test-pattern generation. For quiescent drain current, a parameter for fault detection, the group uses PowerFault-IDDQ, from Synopsys, of which Systems Science, the originator, is now a part. The tool set has been helpful and cut down on time needed for post-scan optimization and possible timing iterations.
Publication Name: IEEE Spectrum
Subject: Engineering and manufacturing industries
ISSN: 0018-9235
Year: 1999
User Contributions:
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