A new role for e-beam: electron projection

Article Abstract:

Bell Labs' new Scalpel system for electron-beam lithography replaces conventional photolithography to expose IC features on silicon and speeds throughput with a step-and-scan approach. Optical lithography is reaching its limits as the curve of IC productivity becomes steeper than even shrinking wavelengths can keep up with. Scalpel is based on reduction image projection, relying on 100-keV electrons scattered to create contrast. It eliminates optical lithography's inherent diffraction limitation and uses a mask membrane with a low atomic number covered with a layer of material that has a higher atomic number. The Scalpel design team chose to employ a small electron beam measuring 1 mm square at the mask, relatively large for electron beams in general but small compared to an IC. Mechanical overheads are the main limitation on printing speed; the key to faster throughput is wider stripes. Larger die sizes can be printed, and achieving good overlay is simple.

Manufacturing processes, Methods, Integrated circuit fabrication, Lithography, Electron beam, Electron beam lithography

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The fine art of IC design

Article Abstract:

Those designing IC chips with 100 million transistors face such daunting challenges ad creating power and signal distribution systems that effectively handle switching currents, optimizing designs amid power constraints, handling asynchronization and managing design reuse. Today's IC model is slow to build, difficult to analyze and must be rearranged for different types of analysis. Use of CAD tools for optimization will be absolutely necessary by 2005, with designers managing the system of optimizing CAD to achieve global convergence. All VLSI designs will soon embody at least some asynchronous elements, and inaccuracies in timing analysis can invalidate skew and speed savings possible otherwise. Reuse is driven by market forces and demands the design of larger blocks that work in multiple applications. Methodology and CAD do not eliminate the need for more design expertise.

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Power to the package

Article Abstract:

The IC industry's move to line widths as small as 100 nanometers presents new challenges for chip packaging technology, which focuses on how and where the silicon chip is connected into the electronic system. Power input and output, which covers the combined issues of delivering power to a chip and dissipating waste heat, is by far the biggest challenge. Most ICs today use either quad flat packages (QFP) or pluggable pin-grid arrays (PGA); newer techniques include chip-scale package (CSP) and ball-grid array (BGA), both of which use solder balls on the underside of the package to take advantage of the full area beneath the chip. Other design techniques include flip-chip connections and 'space transformers' for dealing with thermal issues. BGA packaging is now the favorite for high-density microprocessors, offering a combination of small size, high speed and high I/O count.

Technology development, Packaging, Semiconductors

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