Test & measurement

Article Abstract:

Integrated circuit testers find themselves scrambling to keep up with advances in chip technology. The bus and clock speeds of the technologies that need to be tested are often much faster than the testing equipment itself. The rise of the system on a chip has posed another problem: Virtual embedded component 'cores' have created the need for a new kind of mixed testing by reintroducing analog components to a digital medium. The IEEE 114901-1990 standard has evolved as a starting point for the new technology. It focuses on the testing of interconnects. IEEE P1500 is under development, and will expand the technology to ensure interoperability and testability of cores from different sources.

Semiconductor Devices, Product standards, safety, & recalls, Electronic Test & Measure Eqp, Standards, Semiconductor device, Electronic components, Standard, Standardization, Technology development, Microcontrollers, Microcontroller, Electronic test device, Integrated circuit design, Electronic test equipment, Circuit design, Institute of Electrical and Electronics Engineers

---

Never miss another shot

Article Abstract:

Tokyo based Kyocera Corp. offers a new technology called RTune in at least three of its cameras by which it takes rapid-fire digital shots with its chip set CleanCapture providing the speed for the shots. The functioning of this new digital chip set developed by NuCore Technology Inc. as well as prices of a few Kyocera camera models are also highlighted.

Japan, Photographic equipment and supplies, Product introduction, New Products/Services, Photographic studios, portrait, Photographic Services, Photography Studios, Portrait, Digital Integrated Circuits, Photographic industry, Kyocera Corp., NuCORE Technology Inc.

---

Testing big chips becomes an internal affair

Article Abstract:

Software products called automatic test pattern generators (ATPGs) have been developed for designing gigahertz chips with many hidden nodes. The process is called test synthesis or design for testability (DFT)and it tryies to find the greatest number of potential faults in each case, maximizing fault coverage. Such chips, with feature sizes at or below 250 nm are arriving and require on-the-chip internal testing capability. Automatic test equipment for such testing would, if it were feasible have an enormous price. The cost of testing would be greater than the cost of fabrication. Special software based on algorithms will try to set up a list of patterns or test vectors, to uncover faults. Companies whose products are discussed include Mentor Graphics, Sysnopsys, ATG Technology, Fluence Technology, which bought memory BIST technology from HPL Inc., IBM, Intellitech, LogicVision, Opmaxx, Intusoft, and SynTest Technologies.

Prepackaged software, Market information - general, Product information, Microprocessor Chips, Integrated Circuits by Function, Electronic Test & Measuring NEC, Semiconductor industry, Computer software industry, Software industry, Software, CPUs (Central processing units), Computer aided design, Applications software, Measuring instruments, Application specific integrated circuits

Similar abstracts:

• Abstracts: Still waiting for nanotube memory chip: Nantero's alternative to flash memory has reached its sell-by date. Magnetoelectronic memories last and last
• Abstracts: Superconducting bearings stand the test of load: bearings and energy storage. Bearing lubricants aim for green
• Abstracts: The wireless last mile: entangled in their copper wires, phone companies may miss out on the broader broadband revolution
• Abstracts: Collaboration nation: as group software assumes a major role in the workplace, will engineers stop talking to each other?
• Abstracts: An integrated inventory model for a single vendor and multiple buyers with ordering cost reduction. An inventory control model using fuzzy logic

This website is not affiliated with document authors or copyright owners. This page is provided for informational purposes only. Unintentional errors are possible.