Annealing of high-k dielectrics
Article Abstract:
Two high-k materials which offer potential for high-density DRAMs are the crystalline ceramic oxides, Ta2O5 and BaxSr1-xTiO3 (BST). The two materials have large dielectric constants as a result of strong ionic polarization. The high-purity firms are deposited using metal-organic chemical vapor deposition process at low temperature (400-500 degrees C) to meet the stringent step coverage standards. The films are then annealed to meet the desired capacitance and leakage current.
Publication Name: Semiconductor International
Subject: Electronics and electrical industries
ISSN: 0163-3767
Year: 1999
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Thin gate oxides promise high reliability
Article Abstract:
Device speed turnaround due to mobility loss is likely to be the most prevalent limitation for the gate oxide scaling of semiconductor devices. When maximizing turnaround speeds, the optimal thickness of SiO2 should be two nm. Such a thickness would be enough for channel lengths of as small as 50 nm. However, when the gate oxide scale is under 1.5 nm, other dielectrics will have to be employed as direct tunneling current rises rapidly when SiO2 thickness goes under 1.5 nm.
Comment:
Device speed turnaround due to mobility loss is a likely limitation for the gate oxide scaling of semiconductor devices
Publication Name: Semiconductor International
Subject: Electronics and electrical industries
ISSN: 0163-3767
Year: 1998
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