NEC to build 300 mm fab in California
Article Abstract:
NEC Electronics of Santa Clara, CA, and NEC Corp. of Tokyo, Japan, will develop a new 300 mm, 150 nm process fab beside its existing facilities in Roseville, CA. The new fab is expected to cost $1.4 billion in development over the next four years. The new plant, known as the G-Line, will include two stories and about 600,000 square feet of floor space. The new development will bring the company's total operational floor space in the area to 1.3 million square feet. The new line, which will produce high-performance multimedia and system-on-chip semiconductor products, is expected to start operating in 2002.
Comment:
Will develop a new 300 mm, 150 nm process fab beside its existing facilities in Roseville, CA
Publication Name: Semiconductor International
Subject: Electronics and electrical industries
ISSN: 0163-3767
Year: 1998
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Challenges for 300 mm polished wafer manufacturers
Article Abstract:
The high cost of 300 mm polished silicon wafers has discouraged manufacturers from producing the them greater numbers. Industry analysts have reported that engineers and scientists are searching for methods that will produce silicon wafers without the current level of crystallographic damage. Some of the challenges include improving the operation of wire saws, grinding wheels and polishing mechanisms. But new technologies, such as plasma etching, provide some hope for the production of next-generation wafers.
Publication Name: Semiconductor International
Subject: Electronics and electrical industries
ISSN: 0163-3767
Year: 1998
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Comment about this article or add new information about this topic:
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