Options for CVD of dielectrics include low-k materials
Article Abstract:
The semiconductor industry is utilizing a number of methods for depositing dielectric materials by chemical vapor deposition (CVP). The two well-known methods for dielectric gap applications are the tetraethoxysilane (TEOS)-ozone and the high-density plasma CVD (HDP-CVD). The HDP-CVD films are compressive and dry which lend themselves well to multiple metal layer applications such as microprocessors. The system is plasma-based which provides the advantage of requiring fewer process steps but is more costly than a TEOS-ozone system. The TEOS-ozone system is utilized in many DRAM applications and since the market is more cost effective, its equipment costs less.
Comment:
The semiconductor industry is utilizing numerous methods for depositing dielectric materials by chemical vapor deposition (CVD)
Publication Name: Semiconductor International
Subject: Electronics and electrical industries
ISSN: 0163-3767
Year: 1998
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Wafer-level CSP incubator formed
Article Abstract:
Startup technology development company Decision Track is planning to tap opportunities in wafer-level packaging. The company plans to help suppliers to the chip-scale packaging and interconnect infrastructure to develop new businesses in device design, manufacturing, logistics and materials in support of water-level packaging. The addition of interconnect layers offers opportunities for wafer-level packaging to boost the high-performance power and ground distribution on the IC and routing critical nets in the package interconnect layers.
Publication Name: Semiconductor International
Subject: Electronics and electrical industries
ISSN: 0163-3767
Year: 1999
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Passives require active design approach
Article Abstract:
The codesign of passive devices together with the chip and package has gained more attention due to the need for rf devices in products such as cellular phones and other mobile equipment. RF modules have to be made as multichip modules because of the need to put together signal processing, memory and mixing functions in a single module. The design of a module should be the responsibility of an IC manufacturer to ensure effective global optimization of a module.
Publication Name: Semiconductor International
Subject: Electronics and electrical industries
ISSN: 0163-3767
Year: 2000
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